Field of the Disclosure
Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operations including locking out high conduction current memory cells of the memory devices.
Description of the Related Art
In order to improve read and program performance of memory devices, multiple charge storage elements or memory transistors in an array are read or programmed in parallel. Thus, a “page” of memory elements are read or programmed together. Both reading and verifying operations are performed by executing one or more sensing cycles in which the conduction current or threshold voltage of each memory cell of the page is determined relative to a demarcation value. In general, if the memory is partitioned into n states, there will be at least n−1 sensing passes or levels to resolve all possible memory states. In many implementations, each sensing cycle may also involve two or more passes or levels.
Power consumption is one important consideration of memory devices. With massively parallel sensing, the number of memory cells with conduction current flow will compound. In addition, power may also be consumed in constant voltage bit line schemes which requires a precharge operation during sensing.
Therefore, there is a need for high performance and high capacity non-volatile memory devices with reduced power consumption during sensing operations.